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general description the MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reduc- ing the serial data rate. the data enable input determines when the video or control data is serialized. the MAX9217 pairs with the max9218 deserializer to form a complete digital video serial link. interconnect can be controlled-impedance pc board traces or twisted- pair cable. proprietary data encoding reduces emi and provides dc balance. dc balance allows ac-coupling, providing isolation between the transmitting and receiv- ing ends of the interface. the lvds output is internally terminated with 100 ? . esd tolerance is specified for iso 10605 with 10kv contact discharge and 30kv air discharge. the MAX9217 operates from a +3.3v core supply and features a separate input supply for interfacing to 1.8v to 3.3v logic levels. this device is available in 48-lead thin qfn and tqfp packages and is specified from -40? to +85?. applications navigation system display in-vehicle entertainment system video camera lcd displays features proprietary data encoding for dc balance and reduced emi control data sent during video blanking five control data inputs are single-bit-error tolerant programmable phase-shifted lvds signaling reduces emi output common-mode filter reduces emi greater than 10m stp cable drive wide 2% reference clock tolerance iso 10605 esd protection separate input supply allows interface to 1.8v to 3.3v logic +3.3v core supply space-saving thin qfn and tqfp packages -40 c to +85 c operating temperature MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer ________________________________________________________________ maxim integrated products 1 rng0 rng1 v cclvds out+ out- lvds gnd lvds gnd cmf pwrdwn v ccpll pll gnd mod1 gnd v ccin rgb_in10 rgb_in11 rgb_in12 rgb_in13 rgb_in14 rgb_in15 rgb_in16 rgb_in17 cntl_in0 cntl_in1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd v cc cntl_in2 cntl_in3 cntl_in4 cntl_in5 cntl_in6 cntl_in7 cntl_in8 de_in pclk_in mod0 tqfp MAX9217 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 rgb_in9 rgb_in8 rgb_in7 rgb_in6 rgb_in5 rgb_in4 rgb_in3 rgb_in2 rgb_in1 rgb_in0 v cc gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 MAX9217 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 rng0 rng1 v cclvds out+ out- lvds gnd lvds gnd cmf pwrdwn v ccpll pll gnd mod1 gnd v ccin rgb_in10 rgb_in11 rgb_in12 rgb_in13 rgb_in14 rgb_in15 rgb_in16 rgb_in17 cntl_in0 cntl_in1 gnd v cc cntl_in2 cntl_in3 cntl_in4 cntl_in5 cntl_in6 cntl_in7 cntl_in8 de_in pclk_in mod0 thin qfn-ep rgb_in9 rgb_in8 rgb_in7 rgb_in6 rgb_in5 rgb_in4 rgb_in3 rgb_in2 rgb_in1 rgb_in0 v cc gnd top view part temp range pin- package pkg code MAX9217ecm -40 c to +85 c 48 tqfp c48-5 MAX9217etm -40 c to +85 c 48 thin qfn-ep* t4866-1 pin configurations ordering information 19-3558; rev 2; 10/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad.
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc_ = +3.0v to +3.6v, r l = 100 ? 1%, pwrdwn = high, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25 c.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc_ to _gnd........................................................-0.5v to +4.0v any ground to any ground...................................-0.5v to +0.5v out+, out- to lvds gnd ...................................-0.5v to +4.0v out+, out- short circuit to lvds gnd or v cclvds .............................................................continuous out+, out- short through 0.125f (or smaller), 25v series capacitor..........................................-0.5v to +16v rgb_in[17:0], cntl_in[8:0], de_in, rng0, rng1, mod0, mod1, pclk_in, pwrdwn , cmf to gnd......................-0.5v to (v ccin + 0.5v) continuous power dissipation (t a = +70 c) 48-lead tqfp (derate 20.8mw/ c above +70 c) ....1667mw 48-lead thin qfn (derate 37mw/ c above +70 c) .2963mw esd protection human body model (r d = 1.5k ? , c s = 100pf) all pins to gnd................................................................. 2kv iso 10605 (r d = 2k ? , c s = 330pf) contact discharge (out+, out-) to gnd..................... 10kv air discharge (out+, out-) to gnd............................. 30kv storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units single-ended inputs (rgb_in[17:0], cntl_in[8:0], de_in, pclk_in, pwrdwn , rng_, mod_) v ccin = 1.71v to <3v 0.65v ccin v ccin + 0.3 high-level input voltage v ih 2 v ccin + 0.3 v v ccin = 1.71v to <3v -0.3 0.3v ccin low-level input voltage v il -0.3 +0.8 v input current i in v in = -0.3v to (v ccin + 0.3v), v ccin = 1.71v to 3.6v, pwrdwn = high or low -70 +70 a input clamp voltage v cl i cl = -18ma -1.5 v lvds outputs (out+, out-) differential output voltage v od figure 1 250 335 450 mv change in v od between complementary output states ? v od figure 1 20 mv common-mode voltage v os figure 1 1.125 1.29 1.375 v change in v os between complementary output states ? v os figure 1 20 mv output short-circuit current i os v out+ or v out- = 0 or 3.6v -15 8 +15 ma magnitude of differential output short-circuit current i osd v od = 0 5.5 15 ma out+ = 0, out- = 3.6v output high-impedance current i oz pwrdwn = low or v cc_ = 0 out+ = 3.6v, out- = 0 -1 +1 a
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer _______________________________________________________________________________________ 3 ac electrical characteristics (v cc_ = +3.0v to +3.6v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25 c.) (note 4) parameter symbol conditions min typ max units pclk_in timing requirements clock period t t figure 2 28.57 333.00 ns clock frequency f clk 335mhz clock frequency difference from deserializer reference clock ? f clk -2 +2 % clock duty cycle dc t high /t t or t low /t t, figure 2 35 50 65 % clock transition time t r , t f figure 2 2.5 ns switching characteristics output rise time t rise 20% to 80%, v od 250mv, modulation off, figure 3 215 350 ps output fall time t fall 80% to 20%, v od 250mv, modulation off, figure 3 206 350 ps input setup time t set figure 4 3 ns input hold time t hold figure 4 3 ns serializer delay t sd figure 5 3.15 x t t 3.2 x t t ns pll lock time t lock figure 6 16385 x t t ns power-down delay t pd figure 7 1 s dc electrical characteristics (continued) (v cc_ = +3.0v to +3.6v, r l = 100 ? 1%, pwrdwn = high, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units differential output resistance r o 78 110 147 ? 3mhz 15 25 5mhz 18 25 10mhz 23 28 20mhz 33 39 worst-case supply current i ccw r l = 100 ? 1%, c l = 5pf, continuous 10 transition words, modulation off 35mhz 50 70 ma power-down supply current i ccz (note 3) 50 a
worst-case pattern supply current vs. frequency MAX9217 toc01 frequency (mhz) supply current (ma) 31 27 23 19 15 11 7 10 20 30 40 50 60 0 335 typical operating characteristics (t a = +25 c, v cc_ = +3.3v, r l = 100 ? , modulation off, unless otherwise noted.) MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc_ = +3.0v to +3.6v, r l = 100 ? 1%, c l = 5pf, pwrdwn = high, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25 c.) (note 4) parameter symbol conditions min typ max units 700mbps data rate, cmf open, figure 8 22 70 peak-to-peak output offset voltage v osp-p 700mbps data rate, cmf 0.1f to ground, figure 8 12 50 mv note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v od , ? v od , and ? v os . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are production tested at t a = +25 c. note 3: all lvttl/lvcmos inputs, except pwrdwn at 0.3v or v ccin - 0.3v. pwrdwn is 0.3v. note 4: ac parameters are guaranteed by design and characterization and are not production tested. limits are set at 6 sigma.
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer _______________________________________________________________________________________ 5 pin description pin name function 1, 13, 37 gnd input buffer supply and digital supply ground 2v ccin input buffer supply voltage. bypass to gnd with 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 3 10, 39 48 rgb_in[17:0] lvttl/lvcmos red, green, and blue digital video data inputs. eighteen data bits are loaded into the input latch on the rising edge of pclk_in when de_in is high. internally pulled down to gnd. 11, 12, 15 21 cntl_in[8:0] lvttl/lvcmos control data inputs. control data are latched on the rising edge of pclk_in when de_in is low. internally pulled down to gnd. 14, 38 v cc digital supply voltage. bypass to gnd with 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 22 de_in lvttl/lvcmos data enable input. logic-high selects rgb_in[17:0] to be latched. logic-low selects cntl_in[8:0] to be latched. de_in must be switching for proper operation. internally pulled down to gnd. 23 pclk_in lvttl/lvcmos parallel clock input. latches data and control inputs and provides the pll reference clock. internally pulled down to gnd. 24 mod0 lvttl/lvcmos modulation rate input. selects the phase-modulation step size. internally pulled down to gnd. 25 mod1 lvttl/lvcmos modulation rate input. selects the phase-modulation step size. internally pulled down to gnd. 26 pll gnd pll supply ground 27 v ccpll pll supply voltage. bypass to pll gnd with 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 28 pwrdwn lvttl/lvcmos power-down input. internally pulled down to gnd. 29 cmf common-mode filter. optionally connect a capacitor between cmf and ground to filter common-mode switching noise. 30, 31 lvds gnd lvds supply ground 32 out- inverting lvds serial data output 33 out+ noninverting lvds serial data output 34 v cclvds lvds supply voltage. bypass to lvds gnd with 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 35 rng1 lvttl/lvcmos frequency range select input. set to the frequency range that includes the pclk_in frequency as shown in table 3. internally pulled down to gnd. 36 rng0 lvttl/lvcmos frequency range select input. set to the frequency range that includes the pclk_in frequency as shown in table 3. internally pulled down to gnd. ep gnd exposed pad (thin qfn package only). connect thin qfn exposed pad to pc board gnd.
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 6 _______________________________________________________________________________________ functional diagram MAX9217 timing and control dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 out+ out- cmf mod0 mod1 pll par-to-ser out- v od v os gnd r l / 2 r l / 2 out+ out- out+ (out+) - (out-) v os (-) v os (+) ((out+) + (out-)) / 2 v os (-) v od (-) v od (-) v od = 0v ? v os = | v os (+) - v os (-) | ? v od = | v od (+) - v od (-) | v od (+) figure 1. lvds dc output load and parameters
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer _______________________________________________________________________________________ 7 v ilmax t high t low t t t r t f v ihmin pclk_in figure 2. parallel clock requirements out- c l c l r l out+ t fall 20% 20% (out+) - (out-) 80% 80% t rise figure 3. output rise and fall times v ihmin v ihmin v ihmin v ilmax v ilmax v ilmax pclk_in rgb_in[17:0] cntl_in[8:0] de_in t hold t set figure 4. synchronous input timing
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 8 _______________________________________________________________________________________ t sd bit 0 bit 19 n n + 3 expanded time scale n + 4 n n + 1 n + 2 n - 1 rgb_in cntl_in pclk_in out_ figure 5. serializer delay v od = 0v high-z v ilmax t lock pwrdwn (out+) - (out-) pclk_in figure 6. pll lock time high-z v ilmax t pd pwrdwn (out+) - (out-) pclk_in figure 7. power-down delay
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer _______________________________________________________________________________________ 9 detailed description the MAX9217 dc-balanced serializer operates at a parallel clock frequency of 3mhz to 35mhz, serializing 18 bits of parallel video data rgb_in[17:0] when the data enable input de_in is high, or 9 bits of parallel control data cntl_in[8:0] when de_in is low. the rgb video input data are encoded using 2 overhead bits, en0 and en1, resulting in a serial word length of 20 bits (table 1). control inputs are mapped to 19 bits and encoded with 1 overhead bit, en0, also resulting in a 20-bit serial word. encoding reduces emi and main- tains dc balance across the serial cable. two transition words, which contain a unique bit sequence, are insert- ed at the transition boundaries of video-to-control and control-to-video phases. control data inputs c0 to c4 are mapped to 3 bits each in the serial control word (table 2). at the deserializer, 2 or 3 bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for c0 to c4. control data that may be visible if an error occurs, such as vsync and hsync, can be connect- ed to these inputs. control data inputs c5 to c8 are mapped to 1 bit each. out- out+ ((out+) + (out-)) / 2 v os(p-p) v os(p-p) 012345678910111213141516171819 en0 en1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 figure 8. peak-to-peak output offset voltage bit 0 is the lsb and is serialized first. en[1:0] are encoding bits. s[17:0] are encoded symbols. table 1. serial video phase word format 012345678910111213141516171819 e n 0c0c0c0c1c1c1c2c2c2c3c3c3c4c4c4c5c6c7c8 bit 0 is the lsb and is serialized first. c[8:0] are the control inputs. table 2. serial control phase word format
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 10 ______________________________________________________________________________________ transition timing the transition words require interconnect bandwidth and displace control data. therefore, control data is not sampled (see figure 9): two clock cycles before de_in goes high. during the video phase. two clock cycles after de_in goes low. the last sampled control data are latched at the deserial- izer control data outputs during the transition and video phases. video data are latched at the deserializer rgb data outputs during the transition and control phases. applications information ac-coupling benefits ac-coupling increases the common-mode voltage to the voltage rating of the capacitor. two capacitors are sufficient for isolation, but four capacitors two at the serializer output and two at the deserializer input pro- vide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and common-mode noise. the MAX9217 serializer can also be dc-coupled to the max9218 deserializer. figure 10 shows an ac-coupled serializer and deserial- izer with two capacitors per link, and figure 11 is the ac-coupled serializer and deserializer with four capaci- tors per link. selection of ac-coupling capacitors see figure 12 for calculating the capacitor values for ac-coupling, depending on the parallel clock frequen- cy. the plot shows capacitor values for two- and four- capacitor-per-link systems. for applications using less than 18mhz clock frequency, use 0.125f capacitors. frequency-range setting rng[1:0] the rng[1:0] inputs select the operating frequency range of the MAX9217 serializer. an external clock with- in this range is required for operation. table 3 shows the selectable frequency ranges and corresponding data rates for the MAX9217. pclk_in cntl_in de_in rgb_in = not sampled by pclk_in control phase control phase transition phase transition phase video phase figure 9. transition timing
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer ______________________________________________________________________________________ 11 MAX9217 par-to-ser timing and control dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 ? v cc 130 ? in out 82 ? 82 ? cmf mod0 rng1 rng0 mod1 max9218 ser-to-par timing and control pll dc balance/ decode 1 0 r/f outen rgb_out lock pwrdwn ref_in pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 ? differential stp cable pll * * *capacitors can be at either end. figure 10. ac-coupled serializer and deserializer with two capacitors per link MAX9217 par-to-ser timing and control dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 ? v cc 130 ? in out 82 ? 82 ? cmf mod0 rng1 rng0 mod1 max9218 ser-to-par timing and control pll dc balance/ decode 1 0 r/f outen rgb_out lock pwrdwn ref_in pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 ? differential stp cable pll figure 11. ac-coupled serializer and deserializer with four capacitors per link
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 12 ______________________________________________________________________________________ phase-modulation setting mod[1:0] the serial output edges can be phase shifted (modulated) to reduce emi. table 4 shows the available settings for phase modulation. two shift amplitudes are available. the parallel clock frequency should be 10mhz or higher for the highest amplitude (mod1 = 1, mod0 = 0). termination the MAX9217 has an integrated 100 ? output-termina- tion resistor. this resistor damps reflections from induced noise and mismatches between the transmis- sion line impedance and termination resistors at the deserializer input. with pwrdwn = low or with the sup- ply off, the output termination is switched out and the lvds output is high impedance. common-mode filter the integrated 100 ? output termination is made up of two 50 ? resistors in series. the junction of the resistors is connected to the cmf pin for connecting an optional common-mode filter capacitor. connect the filter capacitor to ground close to the MAX9217 as shown in figure 13. the capacitor shunts common-mode switch- ing current to ground to reduce emi. rng1 rng0 parallel clock (mhz) serial data rate (mbps) 0 0 3 to 5 60 to 100 0 1 5 to10 100 to 200 1 0 10 to 20 200 to 400 1 1 20 to 35 400 to 700 ac-coupling capacitor value vs. parallel clock frequency MAX9217 fig12 parallel clock frequency (mhz) capacitor value (nf) 33 30 21 24 27 35 50 65 80 95 110 125 140 20 18 36 two capacitors per link four capacitors per link figure 12. ac-coupling capacitor values vs. clock frequency of 18mhz to 35mhz table 3. parallel clock frequency range select mod1 mod0 simulated peak power reduction (db) 0 0 0 (off) 0 1 2.5 1 0 4.5 1 1 (reserved) table 4. modulation rate function table out+ r o / 2 r o / 2 cmf out- c cmf figure 13. common-mode filter capacitor connection
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer ______________________________________________________________________________________ 13 power-down and power-off driving pwrdwn low stops the pll, switches out the integrated 100 ? output termination, and puts the output in high impedance to ground and differentially. with pwrdwn 0.3v and all lvttl/lvcmos inputs 0.3v or v ccin - 0.3v, supply current is reduced to 50a or less. driving pwrdwn high starts pll lock to pclk_in and switches in the 100 ? output termination resistor. the lvds output is not driven until the pll locks. the lvds output is high impedance to ground and 100 ? differen- tial. the 100 ? integrated termination pulls out+ and out- together while the pll is locking so that v od = 0v. if v cc = 0, the output resistor is switched out and the lvds outputs are high impedance to ground and differentially. pll lock time the pll lock time is set by an internal counter. the lock time is 16,385 pclk_in cycles. power and clock should be stable to meet the lock-time specification. input buffer supply the single-ended inputs (rgb_in[17:0], cntl_in[8:0], de_in, rng0, rng1, mod0, mod1, pclk_in, and pwrdwn ) are powered from v ccin . v ccin can be connected to a 1.71v to 3.6v supply, allowing logic inputs with a nominal swing of v ccin . if no power is applied to v ccin when power is applied to v cc , the inputs are disabled and pwrdwn is internally driven low, putting the device in the power-down state. power-supply circuits and bypassing the MAX9217 has isolated on-chip power domains. the digital core supply (v cc ) and single-ended input supply (v ccin ) are isolated but have a common ground (gnd). the pll has separate power and ground (v ccpll and v ccpll gnd) and the lvds input also has separate power and ground (v cclvds and v cclvds gnd). the grounds are isolated by diode connections. bypass each v cc , v ccin , v ccpll , and v cclvds pin with high-frequen- cy, surface-mount ceramic 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. lvds output the lvds output is a current source. the voltage swing is proportional to the termination resistance. the output is rated for a differential load of 100 ? 1%. cables and connectors interconnect for lvds typically has a differential imped- ance of 100 ? . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver.
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer 14 ______________________________________________________________________________________ board layout separate the lvttl/lvcmos inputs and lvds output to prevent crosstalk. a four-layer pc board with separate layers for power, ground, and signals is recommended. esd protection the MAX9217 esd tolerance is rated for human body model and iso 10605. iso 10605 specifies esd toler- ance for electronic systems. the human body model discharge components are c s = 100pf and r d = 1.5k ? (figure 14). the iso 10605 discharge compo- nents are c s = 330pf and r d = 2k ? (figure 15). chip information transistor count: 16,608 process: cmos figure 14. human body esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m ? r d 1.5k ? c s 100pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 50 ? to 100 ? r d 2k ? c s 330pf figure 15. iso 10605 contact-discharge esd test circuit
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer ______________________________________________________________________________________ 15 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32l/48l,tqfp.eps e 1 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm e 2 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm
MAX9217 27-bit, 3mhz-to-35mhz dc-balanced lvds serializer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 48l thin qfn.eps a 1 2 21-0160 package outline, 48l thin qfn 6x6x0.8mm body / 0.4mm lead pitch 4. package length / package width are considered as special characteristic. (s) 1. all dimensions are in mm. angles in degrees. 3. warpage shall not exceed 0.10 mm. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. note : a 2 2 21-0160 package outline, 48l thin qfn 6x6x0.8mm body / 0.4mm lead pitch common dimensions l l1 k k1 s a b e d a2 a1 s b m y l o min. nom. max. n nd ne e t4866-1 pkg. e2 exposed pad variatons d2 code min. nom. max. min. nom. max. 12 12 48 0.300 0.400 0.500 0.400 0.500 0.600 0.350 0.450 0.550 0.250 0.350 0.450 5.900 6.000 6.050 0.400 typ. 5.900 6.000 6.100 0.150 0.200 0.250 0.200 ref. 0.000 -- -- 0.050 0.700 0.750 0.800 4.40 4.30 4.20 4.40 4.30 4.20 7. nd and ne refer to the number of terminals on each d and e side respectively. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 6. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. 5. refer to jedec mo-220.

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